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How to simulate after synthesis in NC launch or NC sim

micro469
Hi there  , If we simulate before synthesis with RTL verilog files ,the output of my design is instataneous . But  i want to simulate it after synthesis to know exact delay incurring between the input  and output . How can i do post synthesis simulation with test bench in NC launch or NC sim.Thanks in advance. 

  •  Hi mirco469,

     gate level simulation has many nuances that are not applicable to behavioral simulation. Delay is one of them. Identifying delay is done more effectively and accurately in your implementation and/or timing tools (synthesis, place & route, timing) Simulators simply annotate the delay provided by the other tools. I suggest you contact your AE for help / training or review the documentation

     regards,

    gh-

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