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Avoid race condition at SPI_slave synthesis

alphus

Hello.

I'm trying to synthesis SPI core, but in the simulation occurs race conditions between signals SPI_CLK and system clock (clk) in "always" block:

always @(posedge clk)

spi_clk_r <= spi_clk;

 

How to avoid race condition in this case? 

thanks 

 

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