How to force a small gate structure during RTL Compiler synthesis?

assign out = in0 ^ in1;
dff dff_0(.CLK(CLK), .in(out), .out(q));
..................
module dff(CLK, in, out);
    input CLK;
    input [127:0] in;
    output reg [127:0] out;

    always@(posedge CLK)
        out <= in;

endmodule

However, after synthesis one additional XOR2 gate is inserted between XOR1 and DFF, i.e., "out" connects to one input of XOR2 and the output of XOR2 connects to "D" input of the DFF. I understand that the tool is doing some optimization related to my other logic. But how can I enforce the gate sequence in my verilog code in this specific case? (XOR1 connect to DFF directly) I am fine with restructuring the code.

BTW: I do not use any timing constraints.