Using multiple libraries - mixed elaboration flow

I have a design in which I am testing multiple (similar) libraries. I have a top-level model in Verilog that references a subdesign twice. I would like to synthesize the subdesign with two different libraries to verify functionality under different test conditions post-fab. The subdesign itself references another design.

Right now, my RTL Compiler .tcl file looks something like this:

set_attribute lib_search_path {libpath1/ libpath2/}

set_attribute library {lib1.lib lib2.lib}

read_hdl -library lib1.lib mid_level_lib1.v bottom_level_lib1.v

read_hdl -library lib2.lib mid_level_lib2.v bottom_level_lib2.v

read_hdl top_level.v

elaborate top_level

synthesize -to_mapped -effort high

The mid and bottom level designs are identical except for the module names.

I assumed (perhaps incorrectly) that telling RC to read in my HDL using a specific library would synthesize it with that library.

I also tried a flow using multiple elaborations, and that really didn't work. It kept complaining of being unable to identify my top-level design. I tried another flow with synthesizing each mid/bottom level design in its respecitve libraries, saving the HDL, and synthesizing the top-level. Unfortunately, this complains of black boxes and "mixed elaboration flow [VLOGPT-652]."

Any help would be greatly appreciated.

P.S. What is the preferred way of including code on the forums? It looks like this forum does not support BBCode.