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RTL compiler error

Jinesh K B

Sir, am getting this message when using RC.After showing this message tool is not responding.My other designs are working fine.But for this program sad1.vhd am getting correct output in NCSIM (also I was able to synthesize the design in xilinx ISE) so what may be the problem.

 Elaborating top-level block 'SAD' from file 'sad1.vhd'.
  Done elaborating 'SAD'.
        Trying carrysave optimization (configuration 1 of 1) on module 'SAD_csa_cluster_104'...
Info    : Done carrysave optimization. [RTLOPT-20]
        : There are 2 CSA groups in module 'SAD_csa_cluster_104'... Rejected.
        Trying carrysave optimization (configuration 1 of 2) on module 'SAD_csa_cluster'...
Info    : Done carrysave optimization. [RTLOPT-20]
        : There are 16 CSA groups in module 'SAD_csa_cluster'... Rejected.
        Trying carrysave optimization (configuration 2 of 2) on module 'SAD_csa_cluster'...
Info    : Done carrysave optimization. [RTLOPT-20]
        : There are 17 CSA groups in module 'SAD_csa_cluster'... Rejected.
        Trying carrysave optimization (configuration 1 of 2) on module 'SAD_csa_cluster'...
Info    : Done carrysave optimization. [RTLOPT-20]
        : There are 2 CSA groups in module 'SAD_csa_cluster'... Accepted.
        Trying carrysave optimization (configuration 2 of 2) on module 'SAD_csa_cluster'...
Info    : Done carrysave optimization. [RTLOPT-20]
        : There are 10 CSA groups in module 'SAD_csa_cluster'... Accepted.
Mapping SAD to gates.

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