Low power flow. State retention problem.

Dear all,

I’m studying the Cadence low power flow, and I need your help with some issues.

 I have written a Common Power Format -CPF- file (version 1.1) with 2 Power Domains. Then I have created a Design in SoC Encounter (v14.13) and executed the loadCPF and commitCPF commands. These commands are executed without any error, and isolation and state retention instances are added to the PDs, in the netlist.

I would like to estimate power consumption of my design at the post-synthesis step. Normally I would synthesize the rtl, simulate the netlist, generate a switching activity VCD file, and  run a RC script which reads the netlist, reads the VCD and generates the power report. Doing so, my script doesn't work, because the commitCPF command doesn't add any power switches to the netlist. Thus RC doesn't know which part of the design should be off, even if I generated the VCD by simulating netlist + CPF.

I have modified my script, which now executes the following commands:

read_cpf –library CPF_file.cpf
read_netlist PG_netlist.v
read_cpf CPF_file.cpf
read_vcd –vcd_module uut –module top_design
report power

It almost works. I say almost because the standard logic in an off PD doesn’t consume static power, but the state retention cells have the same static power consumption regardless the condition of their PD (meaning that they consume the same static power even when they are supposed to be off). According to the state retention cells specification given in the library (tcbn45gsbwpcghvt), I would expect a smaller consumption when their PD is off.

Is it possible to estimate the power consumption of a power gated design at this step of the design flow? If it is possible, what could the problem be?

Thanks for your help