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How to connect a common test port to all the CG cells for clock gating?

Hi,

I am using clock gating during synthesize with RTL compiler. Now I can insert the CG cells, but the 'test' port is connected to GND.

I have a test port 'CG_test_mode', but I don't know how to connect this port to all the test pins of CG cells.

Anybody knows?

Thank you

grasshopper over 9 years ago

Please review LP user guide. You need to set the attribute

lp_clock_gating_test_signal

and prior to its use the command

define_dft test_mode

if not in use already

regards,

gh-
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