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check clock_gating gives 0 gated flip-flops after synthesize

Hi,

I am using RTL compiler to synthesize my design, and I want to implement clock gating in my design. Here is part of the constraint

set_attribute lp_insert_clock_gating true /

read_hdl -v2001 $myfiles ;

elaborate $basename ;

# clock gating constrain

set_attribute lp_clock_gating_prefix {CG_CHAO_}

set_attribute lp_clock_gating_exceptions_aware true /

set_attribute lp_clock_gating_module ICG_posedge [dc::current_design]

synthesize -to_clock_gated

synthesize -to_mapped -effort high

And it works, when I use report clock_gating, I can see about 70% flipflops are gated.

But I want to connect all the 'test' pins of ICG cells to CG_always_on port, so I added several lines before synthesize.

define_dft test_mode -active high [find / -port CG_always_on] -name CG_always_on

set_attr lp_clock_gating_test_signal CG_always_on [dc::current_design]

Then after synthesize -to_clock_gated, check clock_gating gives 579 gated flipflop.

But after synthesize -to_mapped -effort high, check clock_gating gives 0 gated flipflop. In netlist, actually there do have gated flipflops.

What is wrong with this?

after synthesize -to_clock_gated, check clock_gating

after synthesize -to_mapped -effort high, check clock_gating

grasshopper over 9 years ago

Please try 15.x and report back if you still see the same issue

gh-
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zczc99 over 9 years ago

Hello grasshopper,

I tried v14.20-s016_1, still the same. But I don't have v15 version.
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grasshopper over 9 years ago

Not sure what you expect to see here. The report looks correct. Inserting clock gating will not change this report. You can model the latency using set_clock_latency constraint but clocks in RC/Genus are ideal hence nothing to show in the report. Please show the output you would like to see if you disagree

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