clock gating timing report with synthesized ICG cell

Hi guys,

I am using clock gating in cadence RTL compiler, but there is no ICG cell in the library. So I implemented an ICG cell with verilog code, which is active high ICG cell.

module ICG_posedge(
  input ck_in,
  input enable,
  input test,
  output ck_out  

);

reg en1;
wire tm_out, ck_inb;

assign tm_out = enable | test ;
assign ck_inb = ~ck_in;

always @(ck_inb, tm_out)
      if(ck_inb)
        en1 = tm_out;
              
assign ck_out = ck_in & en1;
endmodule


after insertion of  clock gating, the timing report seems didn't take the gating into account.

For example, here the clock stop_HF is the non-gated clock,  but the 2 flops both are clock gated. it seems that the ICG cell is transparent to the timing report, and has no effect on the launch and capture clock path.  

Do I need some constraint to make timing analysis take ICG in to account?



Thank you