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Slow Clock Problem

HS88

Hello everybody

I'm designing a fully synchronous digital block for a biomedical application. Since I have a very slow dynamics in my design, I need a slow clock. So I expect to obtain a small power in the synthesis report (I assume if I decrease the speed of the clock the total power should be decreased). However, when I decrease the input clock (by assigning a large number for -period of my external clock) this error appears on screen:

Unsupported SDC command option. [SDC-201] [create_clock]

The 'create_clock' command on line '7' in the SDC file 'calcium.sdc' only accepts values less than 214748.364 for the '-period' option.

Could not interpret SDC command. [SDC-202] [read_sdc]

        : The 'read_sdc' command encountered an error while processing this command on line '7' of the SDC file 'calcium.sdc': create_clock -name clk -period 125000000 [get_ports 'clk'].

The error stems from the large number that I have dedicated to -period in SDC file. I dont know how to define a slow clock for my design and check the coressponding power and area!

Kind regards,

HS88.

 Could not interpret SDC command. [SDC-202] [read_sdc]        : The 'read_sdc' command encountered an error while processing this command on line '7' of the SDC file 'calcium.sdc': create_clock -name clk -period 125000000 [get_ports '

  • Hi Hamid,

    power analysis will use clocks only in the absence of activity for the clocks. In other words, if you set the corresponding activity attributes on the clocks or use an activity file which includes the clocks, the SDC definition for those clocks will be of no consequence to power analysis. The solution therefore would be to use no clock definition or a period within the range for optimization purposes and then ensure you have the accurate activity in your activity file or through attributes such that power reporting will leverage those and your analysis will be more accurate

    hope this helps,

    gh-

  • Really?? So, how does the power analysis calculate the dynamic power (switching power component) in rc compiler? I disagree because when I decrease the clock period within the range, as I expect, total power consumption is also decreased. So, I want to decrease the clock speed as much as possible to reduce the corresponding power!

  • Hi Hamid,

    if no activity file is provided or you are not explicitly setting the corresponding attributes, the SDC is used to determine the toggle of the clock signals  which sounds like what you are seeing

    gh-

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