Scannable DFT shadow-logic insertion with register sharing around FIFOs by adding clock gating on main test clock

Dear all,

I'm currently trying to add scan-chain testability to a design that includes memories implemented with FIFOs. All FIFOs in the design are described at RTL-level using FlipFlops as basic storage elements, hence all these memories are fully-synthesized along with the remaining top-level logic. Since I'm not interested in replacing all FlipFlops of FIFOs with scannable FlipFlops part of the scan-chain, I'm trying to insert shadow logic around them using the insert_dft shadow_logic command. Furthermore I'm only interested in by-passing all FIFOs inputs (my application doesn't require MBIST features for FIFO inputs). Nevertheless I want to make at least FIFOs outputs scannable. Hence my choice was to add scannable shadow-logic with register sharing as described in Design for Test in Encounter RTL Compiler documentation, pp. 220-224. Everything in the Cadence recommended flow works fine up to final scan-chain connection with a satisfactory percentage of ATPG coverage. At the end of the synthesis flow all FIFOs outputs are properly multiplexed with insertion of additional scannable-FlipFlops.

Due to a pad-count limited design the test clock adopted for the scan-chain and defined during the DFT setup is simply the main system clock. Indeed, with such a flow all extra-FlipFlops added by shadow-logic insertion introduce a lot of unwanted extra switching-power due to shadow FlipFlops always connected to the main clock. As a result, I would like to add clock gating to all extra FlipFlops inserted by RTL Compiler during shadow-logic insertion around FIFOs. I tried to perform this at RTL-level by hand, thus I've added an extra, unconnected input port clk_shadow in my design, which in turn is the main system/test clock with a test-mode controlled vetoing  (clock gating is performed in the top-level wrapper with a dedicated latch/and block, I dont't care for the moment about this) . The clk_shadow signal is defined as an auxiliary test clock during the DFT setup, along with the main system/test clock clk :

define_dft \
   test_clock                       \
   -name              scan_clk      \
   -period            25000.0       \
   clk

define_dft \
   test_clock                       \
   -name              shadow_clk    \
   -period            25000.0       \
   -controllable                    \
   clk_shadow

Since at the end of the flow I want to connect all scannable-FlipFlops into a unique scan-chain (including shadow-logic FlipFlops) both clocks are declared as part of the same test-clock domain

set_compatible_test_clocks -all

as suggested in

community.cadence.com/.../24651

After generic synthesis I run the insert_dft shadow_logic command and I specify as test clock the clk_shadow signal, as follows:

insert_dft \
   shadow_logic                                \
   -mode             share                     \
   -around           [find / -instance Fifo*]  \
   -test_control     scan_mode                 \
   -test_clock_pin   clk_shadow

After mapped synthesis I've two scan chains in my design, the first one directly driven by the system/test clock, the second one driven by the "clock-gated by hand at top-level" shadow-logic clock. Finally I run the connect_scan_chains command to merge scan-chains and thanks to the fact that the two clocks are into the same clock domain all extra shadow-logic scannable FlipFlops are connected into a unique scan-chain with others scannable FlipFlops driven by the system/test clock.

Actually, I'm not happy with such a solution that requires extra "tweaking" to RTL. I had a look to the insert_dft scan_power_gating command but its effective usage and application is not clear to me.

Can anyone suggest me the right way to add clock gating to all extra-FlipFlops part of a shadow logic structure?

Thanks in advance

Luca