• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Logic Design
  3. Synthesis in RTL Compiler Lint report

Stats

  • Locked Locked
  • Replies 1
  • Subscribers 62
  • Views 14796
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Synthesis in RTL Compiler Lint report

MickeySingh
MickeySingh over 8 years ago

Hi,

I am new to synthesis and trying to learn.

I am reviewing Lint report from RTL compiler and it's telling that there are few clock pins in my design that are are either unconnected or driven by a logic constant.

These clocks have been defined in the constraints file properly and the also the clock report shows that these are the clocks with 50% duty cycle.

What can be the reason for that?

Regards,

Mickey

  • Cancel
Parents
  • grasshopper
    grasshopper over 8 years ago
    Hi Mickey,

    Let me preface this by saying we can only speculate since there is no log content to be certain what we are talking about.
    Most likely reason is cos' you have some kind of error in you RTL where a number of flops did not have the clock pin connected. The tool is not saying anything about the clock definition. It is trying to tell you that for some reason, the clock never made it to the flops in question. Could be simply miss-connected in RTL, a clock-gater that is always disabled, etc. Hard to provide more insight without more details but I suggest you take a careful look at RTL and log messages and likely you will find the answer in those 2

    gh-
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • grasshopper
    grasshopper over 8 years ago
    Hi Mickey,

    Let me preface this by saying we can only speculate since there is no log content to be certain what we are talking about.
    Most likely reason is cos' you have some kind of error in you RTL where a number of flops did not have the clock pin connected. The tool is not saying anything about the clock definition. It is trying to tell you that for some reason, the clock never made it to the flops in question. Could be simply miss-connected in RTL, a clock-gater that is always disabled, etc. Hard to provide more insight without more details but I suggest you take a careful look at RTL and log messages and likely you will find the answer in those 2

    gh-
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information