Module name change after synthesis in RTL compiler

Hi,

I am trying to synthesize VHDL files using RTL compiler and created the netlist file. My design is hierarchical with submodules. However, the netlist created with a submodule name. Is it due to some optimization? How can I change this? My script is as below

set_attr lib_search_path /cad/FOUNDRY/digital/90nm/dig/lib

#set_attr hdl_search_path ../rtl/
set_attr library /cad/FOUNDRY/digital/90nm/dig/lib/slow.lib

read_hdl -vhdl {/home/manideepam/NOC/my_package.vhd /home/manideepam/NOC/my_switchcontrol.vhd /home/manideepam/NOC/my_buffer.vhd /home/manideepam/NOC/my_crossbar.vhd /home/manideepam/NOC/RouterBL.vhd /home/manideepam/NOC/RouterBC.vhd /home/manideepam/NOC/RouterBR.vhd /home/manideepam/NOC/RouterCC.vhd /home/manideepam/NOC/RouterCL.vhd /home/manideepam/NOC/RouterCR.vhd /home/manideepam/NOC/RouterTL.vhd /home/manideepam/NOC/RouterTR.vhd /home/manideepam/NOC/RouterTC.vhd /home/manideepam/NOC/NOC.vhd}

elaborate NOC
read_sdc NOC_constraints.sdc
#read_sdc constraints_top.sdc
check_design NOC -unresolved
synthesize -to_mapped -effort medium

#write_sdf -timescale ns -nonegchecks -recrem split -edges check_edge > delays.sdf
write_hdl NOC > NOC_netlist.v
write_sdc NOC > NOC_rc_sdc.sdc
write_script NOC > NOC_rc_sdc.g

report power > NOC_power.rep
report timing -lint > NOC_timing.rep
report gates > NOC_cell.rep
report area > NOC_area.rep
gui_show