port array synthesis

Dear all,

in my design I use as an input port the following statement

input logic [15:0] d [15:0]

This statement is supposed to be the input of a 16 to 1 / 16
bits wide inputs multiplexer.

Obviously synthesis is going pretty well since I get an output
netlist. Though when I try to simulate using the same testbench I used
for pre-synthesis simulation, using the following statement for
connectio, xcelium throw an error

// ---------------------------------------------------------------------
// internal testbench code sample
// ---------------------------------------------------------------------
logic [n-1:0] data_write [n-1:0];
reg_shift_milpisso rs0 (.d(data_write),.*);


// ---------------------------------------------------------------------
// xcelium error
// ---------------------------------------------------------------------
xrun(64): 17.10-s010: (c) Copyright 1995-2018 Cadence Design Systems, Inc.
xrun: *N,CLEAN: Removing existing directory ./xcelium.d.
Caching library 'worklib' ....... Done
Elaborating the design hierarchy:
reg_shift_milpisso rs0 (.d(data_write),.*);
|
xmelab: *E,CUVPOM (./reg_shift_milpisso_tb.sv,28|28): Port name 'd' is
invalid or has multiple connections.  xrun: *E,ELBERR: Error during
elaboration (status 1), exiting.

the synthesis resulting netlist  is the following

// ---------------------------------------------------------------------
// synthesis netlist sample
// ---------------------------------------------------------------------

// Generated by Cadence Genus(TM) Synthesis Solution 16.23-s049_1
// Generated on: Jul 16 2018 14:49:52 CEST (Jul 16 2018 12:49:52 UTC)

// Verification Directory fv/reg_shift_milpisso

module reg_shift_milpisso(clock, reset, op, sel, \d[0] , \d[1] , \d[2]
, \d[3] , \d[4] , \d[5] , \d[6] , \d[7] , \d[8] , \d[9] , \d[10] ,
\d[11] , \d[12] , \d[13] , \d[14] , \d[15] , q);
input clock, reset;
input [1:0] op;
input [3:0] sel;
input [15:0] \d[0] , \d[1] , \d[2] , \d[3] , \d[4] , \d[5] , \d[6] ,
\d[7] , \d[8] , \d[9] , \d[10] , \d[11] , \d[12] , \d[13] ,
\d[14] , \d[15] ;


My question is then the following one, can I use this kind of ports
without having the escaped ports ?

thank you for your time and consideration.

Olivier