Irun driver contention with SystemVerilog port defaults (15.20.001)

Hi folks,

I am simulating a mixed language design with Irun 15.20.001 with DUT toplevel being Verilog and lower level files being SystemVerilog and VHDL. Irun is seeing driver contention on SystemVerilog ports that have defaults defined. For example, I have a clock input port in a SV file that has a default of '0'. When I try to force this clock from the DUT, it goes X due to the default value contention. I tried running the simulation with various Irun systemverilog options from sysv2005 to sysv2009 to disable_sem2009 with no difference. What could be the issue here and how can I resolve it? Thanks.