I am trying to synthesize my design using Cadence RTL compiler Ultra. However, it invariably crashes after synthesizing to generic gates in the "Multi-threaded Virtual Mapping" Phase. I am using the version :RC14.28 - v14.20-s067_1 (64-bit), built Jun 22 2016
The design does not have any non-synthesizable constructs that were reported by RTL Compiler but there are multiple memory (register array) modules in my RTL that I removed from the RTL list so it references them as black boxes. I am not using gui. Script doesn't contain any special constraints just a clock definition, lp_insert_clock_gating true and hdl_max_loop_limit 2048. It just quits the process and goes back to the rc prompt without giving any error. Any help will be deeply appreciated. Thanks!