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RTL synthesis fault

Dear All,
While I am trying to synthesis from Verilog file with Genus, I find some faults. After I set my files, rest of my Tcl file is like at below.

elaborate

# Apply Constraints
set clock [define_clock -period ${delay} -name ${clkpin} [clock_ports]]
external_delay -input 0 -clock ${clkpin} [find / -port ports_in/*]
external_delay -output 0 -clock ${clkpin} [find / -port ports_out/*]
check_design -all

#Synthesis
synthesize -to_generic -eff medium
synthesize -to_mapped -eff medium -no_incr
synthesize -to_mapped -eff medium -incr
synthesize -to_mapped
#syn_gen
#syn_map
#syn_opt

#Reports
report timing > ./rep/${runDesign}_${delay}mHz_timing.rep
report gates > ./rep/${runDesign}_${delay}mHz_cell.rep
report power > ./rep/${runDesign}_${delay}mHz_power.rep
report area > ./rep/${runDesign}_${delay}mHz_area.rep

gui_show

When I use "synthesize ....." options under "#Synthesis", end of my log file as like below.

Info    : Pre-processed datapath logic. [DPOPT-6]
        : No pre-processing optimizations applied to datapath logic in 'pbs_gen_n_6'.
Info    : Optimizing datapath logic. [DPOPT-1]
        : Optimizing datapath logic in 'pbs_gen_n_6'.
Info    : Implementing datapath configurations. [DPOPT-3]
        : Implementing datapath configurations for 'CDN_DP_region_70'
Info    : Done implementing datapath configurations. [DPOPT-4]
        : Selected 'very_fast' configuration 4 for module 'CDN_DP_region_70'.
          Optimizations applied to 'very_fast' configuration:
            rewriting(0), factoring(0), sharing(0), cmultcse(0), downsizing(0), speculation(0)
Info    : Implementing datapath configurations. [DPOPT-3]
        : Implementing datapath configurations for 'CDN_DP_region_69'
Info    : Done implementing datapath configurations. [DPOPT-4]
        : Selected 'very_fast' configuration 4 for module 'CDN_DP_region_69'.
          Optimizations applied to 'very_fast' configuration:
            rewriting(0), factoring(0), sharing(0), cmultcse(0), downsizing(0), speculation(0)
Info    : Implementing datapath configurations. [DPOPT-3]
        : Implementing datapath configurations for 'CDN_DP_region_68'
Info    : Done implementing datapath configurations. [DPOPT-4]
        : Selected 'very_fast' configuration 4 for module 'CDN_DP_region_68'.
          Optimizations applied to 'very_fast' configuration:
            rewriting(0), factoring(0), sharing(0), cmultcse(0), downsizing(0), speculation(0)
Info    : Implementing datapath configurations. [DPOPT-3]
        : Implementing datapath configurations for 'CDN_DP_region'
Info    : Done implementing datapath configurations. [DPOPT-4]
        : Selected 'very_fast' configuration 4 for module 'CDN_DP_region'.
          Optimizations applied to 'very_fast' configuration:
            rewriting(0), factoring(0), sharing(0), cmultcse(0), downsizing(0), speculation(0)
Info    : Done optimizing datapath logic. [DPOPT-2]
        : Done optimizing datapath logic in 'pbs_gen_n_6'.
      Removing temporary intermediate hierarchies under pbs_gen_n_6
Sourcing './.pbs_server.xx_177790/pbs_gen_n_6.etf' (Wed Jan 16 18:58:25 +03 2019)...
rdbfname wdbfname effort physical pas design assembly_index
./.pbs_server.xx_177790/pbs_gen_n_6.db ./.pbs_server.xx_177790/pbs_gen_n_6_post.db medium 0 0 /designs/pbs_gen_n_6 -1

Segmentation Fault accessing address ffffffffffffc6a0.

Fatal internal error, code 11 (Segmentation fault)

Dumping stack trace (tid:7fbce9466400/main thread).

Operating System: linux
Product Version:
Build Date:
Executable: /cds/GENUS171/tools.lnx86/synth/bin/64bit/genus
Startup Options: -legacy_ui
Current Directory: /home/user/work/genus/
Stack trace:
Segmentation fault (core dumped)

When I use "syn_gen ....." options, end of my log file as like below.

Info    : Pre-processed datapath logic. [DPOPT-6]
        : No pre-processing optimizations applied to datapath logic in 'pbs_gen_n_6'.
Info    : Optimizing datapath logic. [DPOPT-1]
        : Optimizing datapath logic in 'pbs_gen_n_6'.
Info    : Implementing datapath configurations. [DPOPT-3]
        : Implementing datapath configurations for 'CDN_DP_region_70'
Info    : Done implementing datapath configurations. [DPOPT-4]
        : Selected 'very_fast' configuration 4 for module 'CDN_DP_region_70'.
          Optimizations applied to 'very_fast' configuration:
            rewriting(0), factoring(0), sharing(0), cmultcse(0), downsizing(0), speculation(0)
Info    : Implementing datapath configurations. [DPOPT-3]
        : Implementing datapath configurations for 'CDN_DP_region_69'
Info    : Done implementing datapath configurations. [DPOPT-4]
        : Selected 'very_fast' configuration 4 for module 'CDN_DP_region_69'.
          Optimizations applied to 'very_fast' configuration:
            rewriting(0), factoring(0), sharing(0), cmultcse(0), downsizing(0), speculation(0)
Info    : Implementing datapath configurations. [DPOPT-3]
        : Implementing datapath configurations for 'CDN_DP_region_68'
Info    : Done implementing datapath configurations. [DPOPT-4]
        : Selected 'very_fast' configuration 4 for module 'CDN_DP_region_68'.
          Optimizations applied to 'very_fast' configuration:
            rewriting(0), factoring(0), sharing(0), cmultcse(0), downsizing(0), speculation(0)
Info    : Implementing datapath configurations. [DPOPT-3]
        : Implementing datapath configurations for 'CDN_DP_region'
Info    : Done implementing datapath configurations. [DPOPT-4]
        : Selected 'very_fast' configuration 4 for module 'CDN_DP_region'.
          Optimizations applied to 'very_fast' configuration:
            rewriting(0), factoring(0), sharing(0), cmultcse(0), downsizing(0), speculation(0)
Info    : Done optimizing datapath logic. [DPOPT-2]
        : Done optimizing datapath logic in 'pbs_gen_n_6'.
      Removing temporary intermediate hierarchies under pbs_gen_n_6
Sourcing './.pbs_server.xxx_181030/pbs_gen_n_6.etf' (Wed Jan 16 19:44:50 +03 2019)...
rdbfname wdbfname effort physical pas design assembly_index
./.pbs_server.xxx_181030/pbs_gen_n_6.db ./.pbs_server.xxx_181030/pbs_gen_n_6_post.db medium 0 0 /designs/pbs_gen_n_6 -1
Illegal instruction (core dumped)

They are pretty much same but I just want to share. If you have any idea about it, it will be so helpfull for me.

Parents

Rameen over 4 years ago

occur same issue? Did you find any solution or reason of this error?
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nokta over 4 years ago in reply to Rameen

It is been a long time and I cannot remember exactly but I think its reason was the lack of RAM. Are you trying to synthesis a big design and can you check the RAM while synthesis?

And can you share your RAM size and the address given at the line below in the log file?

Segmentation Fault accessing address XYZ
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nokta over 4 years ago in reply to Rameen

It is been a long time and I cannot remember exactly but I think its reason was the lack of RAM. Are you trying to synthesis a big design and can you check the RAM while synthesis?

And can you share your RAM size and the address given at the line below in the log file?

Segmentation Fault accessing address XYZ
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Rameen over 4 years ago in reply to nokta

yes, I am trying to synthesize big design and the RAM Size of our server is 256GB.Address is 38
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Rameen over 4 years ago in reply to nokta

By the way its not a big design like HPC, You can say that its a small design. So 256GB is much more enough for synthesize
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