I am using Conformal Constraint Designer (Version 17.1) to analyse a SystemVerilog based design.
While performing default HDL checks it finds some violations (issues) in RTL and complains (warnings, etc) about RTL checks and others.
Is there any directive which I can add to RTL (system Verilog) so that particular line of code or signal is ignored or not checked for HDL or RTL checks.
I can set ignore rules in rule manager (gui) but it does not seems effective if code line number changes or new signals are introduced.
What is the best way to customize default_hdl_rules ?
I will be grateful for your guidance.
Thanks for your time.