Hi,

I elaborate my design and then i read SDC constraints on GENUS. Then I run check_timing_intent to check the SDC quality and timing attributes placed on the current design. The result is

Sequential clock pins without clock waveform

The following sequential clock pins have no clock waveform driving them. No
timing constraints will be derived for paths leading to or from these pins.

pin:dig_part_neuromorphic_core/aer_decoder/addr_ack_reg/ena
pin:dig_part_neuromorphic_core/aer_decoder/addr_out_reg[0]/ena
pin:dig_part_neuromorphic_core/aer_decoder/addr_out_reg[1]/ena
... 76 other warnings in this category.
Use the -verbose option for more details.
-------------------------------------------------------------------------------

Lint summary
Unconnected/logic driven clocks 0
Sequential data pins driven by a clock signal 0
Sequential clock pins without clock waveform 79
Sequential clock pins with multiple clock waveforms 0
Generated clocks without clock waveform 0
Generated clocks with incompatible options 0
Generated clocks with multi-master clock 0
Paths constrained with different clocks 0
Loop-breaking cells for combinational feedback 0
Nets with multiple drivers 0
Timing exceptions with no effect 0
Suspicious multi_cycle exceptions 0
Pins/ports with conflicting case constants 0
Inputs without clocked external delays 0
Outputs without clocked external delays 0
Inputs without external driver/transition 0
Outputs without external load 0
Exceptions with invalid timing start-/endpoints 0

Total: 79

I don't know what this pin ena is. All 79 warnings are about pin ena on various modules. What constraint should I add to overcome this warning?
These are my constraints:

set_time_unit -picoseconds 1
set_load_unit -picofarads 1
create_clock [get_ports in_clk] -name clk1 -period 100000000 -waveform {0 2.5}
set_input_delay 10 -clock clk1 [all_inputs]
set_output_delay 10 -clock clk1 [all_outputs]

set_load 1.5 -min -pin_load [get_ports {out_addr_ack}]
set_load 3 -max -pin_load [get_ports {out_addr_ack}]
set_load 1.5 -min -pin_load [get_ports {out_neuron_1}]
set_load 3 -max -pin_load [get_ports {out_neuron_1}]
set_load 1.5 -min -pin_load [get_ports {out_neuron_2}]
set_load 3 -max -pin_load [get_ports {out_neuron_2}]
set_load 1.5 -min -pin_load [get_ports {out_neuron_3}]
set_load 3 -max -pin_load [get_ports {out_neuron_3}]
set_load 1.5 -min -pin_load [get_ports {out_neuron_4}]
set_load 3 -max -pin_load [get_ports {out_neuron_4}]
set_load 1.5 -min -pin_load [get_ports {out_neuron_5}]
set_load 3 -max -pin_load [get_ports {out_neuron_5}]
set_load 1.5 -min -pin_load [get_ports {out_neuron_6}]
set_load 3 -max -pin_load [get_ports {out_neuron_6}]
set_load 1.5 -min -pin_load [get_ports {out_neuron_7}]
set_load 3 -max -pin_load [get_ports {out_neuron_7}]
set_load 1.5 -min -pin_load [get_ports {out_neuron_8}]
set_load 3 -max -pin_load [get_ports {out_neuron_8}]

set_input_transition 0.5 [get_ports {in_addr_req}]
set_input_transition 0.5 [get_ports {in_address}]
set_input_transition 0.5 [get_ports {in_cs_write}]
set_input_transition 0.5 [get_ports {in_data_write}]
set_input_transition 0.5 [get_ports {in_data_write}]
set_input_transition 0.5 [get_ports {in_mode}]
set_input_transition 0.5 [get_ports {in_reset}]
set_input_transition 0.5 [get_ports {in_reset_2}]
set_input_transition 0.5 [get_ports {in_stop_timer}]