Hi to you all,I'm new to genus and this forum. I'm working on a mixed-signals chip and my company is using the cadence tool.I'm trying to use to genus 20.1 to synthesize our RTL and trying to build a workflow.One problem I have is that I have no idea on how to deal with analog signals and power supplies. Is there a way to "flag" them so that genus can properly recognize those signals.
For exmaple, so far I reached end of elaboration for my design, and in the .log file I noticed the following lines:
Checking for analog nets...Check completed for analog nets.
But in my RTL I didn't specified any analog net. Whart is genus checking for?
I searched the decumentation for this: Genus User Guide, Genus HDL Modeling Guide and the Genus Command Reference with no luck.Is there something I could read up to learn about this topic, wich is new to me?