• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Logic Design
  3. VHDL-613 error inside declarative region

Stats

  • Locked Locked
  • Replies 0
  • Subscribers 62
  • Views 12807
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

VHDL-613 error inside declarative region

carlosgewehr
carlosgewehr over 4 years ago

I have a deeply parameterized VHDL design, in which several submodules are instantiated within a top level module, each with different parameters. For the sake of better code organization, i have experimented with using a JSON file to define these parameters, reading this file within the top module, and then instantiating the submodules with the associated parameters.

The means to read and parse this JSON file are obviously not synthesizeable, since they require string manipulations and whatnot. However, since these operations happen entirely within the declarative region of my VHDL top module (assignments to constants from function calls), it was my understanding that this wouldn't be a problem for synthesis, since the instantiated submodules are all synthesizeable, and, as said before, the non-syntesizeable part of the whole thing is confined to the declarative region of the top level module, implying that the non-synthesizeable portion of the design would not be "executed at run-time", and thus, not creating any problems for Genus. Through the "read_hdl" command, all submodules and packages in which the JSON-related functions are defined are processed with no synthesizeability-related errors, except for warnings concerning assertions, which is not relevant in ths case.

However, when using the "read_hdl" command on the top level module source file, the VHDL-613 error (unsuported predefined attribute) is thrown inside the non-synthesizeable code involved in reading the parameters from the JSON file, associated to using the 'Image and 'Value attributes for manipulating the parsed JSON info, despite this happening inside the declarative region.

Only this error (VHDL-613) is observed, and not anything else concerning the (non-synthesizeable) file manipulations, which leads me to believe this might be a problem with Genus, perhaps not checking if the non-supported attribute is not accessed in "run-time", seeing as this probably happens in other similar situations, namely opening and reading a file, which are also not synthesizeable, but seem to be ignored.

In conclusion, is this a bug or an intended feature (im on v18.1)? My attemps to go around this issue have been unsuccessful so far, and if this indeed is a feature and not a bug, a major re-write of my design will be necessary.

  • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information