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Community Forums Logic Design UNCONNECTED NETS in GENUS NETLIST!

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UNCONNECTED NETS in GENUS NETLIST!

AireenAmir
AireenAmir over 1 year ago

Hi ,

I have synthesized a design RTL in GENUS and there are UNCONNECTED NETS in the netlist which causes the PnR flow to fail at the placement stage. A portion of the netlist indicating the unconnected nets is as follows:

module DFFRAM_COLS1(CLK, WE, EN, Di, Do, A);
input CLK, EN;
input [3:0] WE;
input [31:0] Di;
input [7:0] A;
output [31:0] Do;
wire CLK, EN;
wire [3:0] WE;
wire [31:0] Di;
wire [7:0] A;
wire [31:0] Do;
wire UNCONNECTED_HIER_Z2, UNCONNECTED_HIER_Z3, UNCONNECTED_HIER_Z4;
DFFRAM_COL4 \COLUMN[0].RAMCOLS (.CLK (CLK), .WE (WE), .EN
(UNCONNECTED_HIER_Z2), .Di (Di), .Do (Do), .A
({UNCONNECTED_HIER_Z4, UNCONNECTED_HIER_Z3, A[5:0]}));
endmodule

Searching the cadence support platform to tackle the issue redirected me to a document where adding the command "set_db write_vlog_unconnected_port_style partial", was mentioned to solve the issue. Adding this to my source file didn't completely remove the UNCONNECTED wire declaration in the module definition of the generated netlist.

module DFFRAM_COLS1(CLK, WE, EN, Di, Do, A);
input CLK, EN;
input [3:0] WE;
input [31:0] Di;
input [7:0] A;
output [31:0] Do;
wire CLK, EN;
wire [3:0] WE;
wire [31:0] Di;
wire [7:0] A;
wire [31:0] Do;
DFFRAM_COL4 \COLUMN[0].RAMCOLS (.CLK (CLK), .WE (WE), .EN (), .Di
(Di), .Do (Do), .A ({UNCONNECTED_HIER_Z4, UNCONNECTED_HIER_Z3,
A[5:0]}));
endmodule

Can somebody help me solve this issue?

Thanks

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  • Rameen
    Rameen over 1 year ago

    did you find the solution?

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