Default settings for cell mapping - Genus Synthesis (Legacy)

I have 2 standard cell libraries, one which has cells operating at 1.8V and the other at 0.3V. The 0.3V cells have a lot more delay than the 1.8V ones. When I synthesize the same design (HDL file) using the 2 different libraries in Genus's legacy UI as follows, I get 2 completely different power and timing reports, which is expected. I also noticed that when mapping to the cells operating at 0.3V, Genus uses a lot more cells than the flow where I use 1.8V cells (less delay)

here's how I am synthesizing the designs:

set_attribute lib_search_path ./library
set_attribute library { type1.lib }

read_hdl design.v
elaborate

synthesize -to_mapped

I wanted to know if the number of cells being taken in case of the larger delay cells is actually because of the delay.
Example:

When I synthesize an 8bit ALU using the 1.8V cells, Genus makes use of 1795 cells, and when I use the 0.3V cells, Genus makes use of 3510 cells.
In this context, cells mean logic gates.

I'm aware that this particular comparison would be based on an unconstrained mapping, and I am aware that I can specify the power intents and delay constraints using CPF and SDC, but on what basis does Genus take 3510 gates for the 0.3V case, and 1795 in the 1.8V case?

Is Genus trying to give me the best power-delay product? or the least possible delay? or least possible power? What is the default setting?

Thanks in advance