How to add logic when compile

Hi all,

I want to run simulation to check case the connection between modules be fixed 0/1 in specific time.

The idea is there will be logic (work same as isolation cell) be inserted in later phase to fixed value between 2 modules in specific time.

But I want to check it in early phase, when run simulation with RTL.

Example:

This checking apply to huge number of connection.

I came up with 2 idea:

1. Using Force command for all net of these net name connection. But there is a problem:

Connection A -> B: force at input of module B, logic inside at input of module A also be forced. I want to check only input of B be forced

2. Using UPF to define Isolation cell between module A and B. This same as my expectation but it is complex.

I wonder Xcelium support any solution for this case.

Thanks and Best regards,