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I have designed my own standard cell library using some commercial process technology. I am trying to synthesize a large design that is implemented as a retimed module whose latency is controlled by some config (The Verilog description is generated using Bluespec that takes config in a YAML file).
When I try to synthesize this design,
Error: Cannot synthesize the inserted flops. [RETIME-105] [retime] Make sure that a suitable library cell is available.
The synthesis tool is Cadence Genus. My guess is that State Retention Synthesis (going by the name) uses retention flops, and the standard cell library has only 2 sequential elements, A DFF with and without an async reset.
I am unable to find documentation about this on the web. I took a look at the Genus user manual but it just tells me -
RETIME-105 Severity Error
Description Cannot synthesize the inserted flops.
What's Next Make sure that a suitable library cell is available.
Any links/answers would be appreciated. Thanks in advance!