Genus : Tool coming out with "Killed"

Snapshot of the error seen.

//=================================

// RTL CODE 

`define UNPACK_3D_ARRAY(D_WIDTH,COLUMNS,ROWS,PK_DEST,PK_SRC) genvar p_unpk_idr; genvar p_unpk_idk; generate for (p_unpk_idr=0; p_unpk_idr<(ROWS); p_unpk_idr=p_unpk_idr+1) begin for(p_unpk_idk=0; p_unpk_idk<(COLUMNS); p_unpk_idk=p_unpk_idk+1) begin assign PK_DEST[p_unpk_idk][p_unpk_idr][D_WIDTH-1:0] = PK_SRC[((D_WIDTH*COLUMNS)*p_unpk_idr+ p_unpk_idk*(D_WIDTH) + (D_WIDTH-1)):(p_unpk_idr*(COLUMNS*D_WIDTH) + p_unpk_idk*(D_WIDTH))]; end end endgenerate

`define UNPACK_ARRAY(PK_WIDTH,PK_LEN,PK_DEST,PK_SRC) genvar p_upkidx_2d; generate for (p_upkidx_2d=0; p_upkidx_2d<(PK_LEN); p_upkidx_2d=p_upkidx_2d+1) begin assign PK_DEST[p_upkidx_2d][((PK_WIDTH)-1):0] = PK_SRC[((PK_WIDTH)*p_upkidx_2d+(PK_WIDTH-1)):((PK_WIDTH)*p_upkidx_2d)]; end endgenerate

`define P_UPK_ARRAY(PK_WIDTH,PK_LEN,PK_DEST,PK_SRC) genvar p_upk_idx; generate for (p_upk_idx=0; p_upk_idx<(PK_LEN); p_upk_idx=p_upk_idx+1) begin assign PK_DEST[p_upk_idx][((PK_WIDTH)-1):0] = PK_SRC[((PK_WIDTH)*p_upk_idx+(PK_WIDTH-1)):((PK_WIDTH)*p_upk_idx)]; end endgenerate

`define PACK_ARRAY(PK_WIDTH,PK_LEN,PK_SRC,PK_DEST) genvar p_pk_idx; generate for (p_pk_idx=0; p_pk_idx<(PK_LEN); p_pk_idx=p_pk_idx+1) begin assign PK_DEST[((PK_WIDTH)*p_pk_idx+((PK_WIDTH)-1)):((PK_WIDTH)*p_pk_idx)] = PK_SRC[p_pk_idx][((PK_WIDTH)-1):0]; end endgenerate

`timescale 1ns/1ps

module product (
clk,
rst_n,
data_in,
dval,
weight,
bias,
ready,
data_out,
done
);

parameter IN_WIDTH = 256;
parameter OUT_WIDTH= 20;
parameter D_WIDTH = 8;

localparam [1:0] IDLE=2'b0, CAPTURE = 2'b1, CALC = 2'b10, PUSH_OUT=2'd3;

input clk;
input rst_n;
input signed [D_WIDTH*IN_WIDTH-1:0] data_in;
input dval;
input signed [D_WIDTH*IN_WIDTH*OUT_WIDTH -1 :0] weight;
input signed [D_WIDTH*OUT_WIDTH -1:0] bias;
output reg signed [D_WIDTH*OUT_WIDTH-1:0] data_out;
output reg done;
output reg ready;

reg calc_completed;

//wire clk;
//wire rst_n;
//wire signed [D_WIDTH*IN_WIDTH-1:0] data_in;
//wire dval;
//wire signed [D_WIDTH*OUT_WIDTH -1:0] bias;
//wire signed [D_WIDTH*IN_WIDTH*OUT_WIDTH -1 :0] weight;

//reg signed [D_WIDTH*OUT_WIDTH-1:0] data_out;

//== Unpack the weights and biases
wire signed [D_WIDTH-1:0] w [IN_WIDTH-1:0][OUT_WIDTH-1:0];
wire signed [D_WIDTH-1:0] b [OUT_WIDTH-1:0];
wire signed [D_WIDTH-1:0] d [IN_WIDTH-1:0];

wire signed [D_WIDTH*OUT_WIDTH-1:0] dout_wire;

integer ii;
integer jj;

reg signed [D_WIDTH*IN_WIDTH-1:0] r_data_in;

reg signed [2*D_WIDTH -1:0] prod;
reg signed [D_WIDTH-1:0] outp [OUT_WIDTH -1:0];
reg signed [D_WIDTH-1:0] temp;

reg [1:0] cur_state, nxt_state;

`UNPACK_3D_ARRAY(D_WIDTH, IN_WIDTH, OUT_WIDTH, w, weight)
`UNPACK_ARRAY (D_WIDTH, OUT_WIDTH, b, bias)
`P_UPK_ARRAY (D_WIDTH, IN_WIDTH, d, r_data_in)
`PACK_ARRAY(D_WIDTH, OUT_WIDTH, outp, dout_wire)

always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
cur_state <= IDLE;
else
cur_state <= nxt_state;
end

always @(cur_state or dval or calc_completed) begin
case (cur_state)
IDLE : begin
if (dval == 0)
nxt_state = IDLE;
else
nxt_state = CAPTURE;
end
CAPTURE : begin
if (dval == 1)
nxt_state = CAPTURE;
else
nxt_state = CALC;
end
CALC : begin
if (calc_completed == 0)
nxt_state = CALC;
else
nxt_state = PUSH_OUT;
end
PUSH_OUT : begin
nxt_state = IDLE;
end
endcase
end

always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
r_data_in <= 0;
ready <= 1;
calc_completed <= 0;
end
else if (dval == 1)
begin
r_data_in <= data_in;
ready <= 0;
end
end

always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
for (ii=0 ; ii < OUT_WIDTH; ii = ii +1) begin
outp[ii] = 0;
end
done <= 0;
end else begin
case (cur_state)
IDLE:
begin
for (ii= 0; ii < OUT_WIDTH; ii = ii +1)
outp[ii] = 0;
done <= 0;
ready <= 1;
calc_completed <= 0;
ii = 0;
jj = 0;
end
CAPTURE:
begin
done <= 0;
end
CALC:
begin
prod= w[jj][ii]*d[jj];
outp[ii] = prod[D_WIDTH+4-1:4] + outp[ii];
if (jj == IN_WIDTH -1) begin
jj = 0;
outp[ii]= outp[ii] + b[ii];
if (ii == OUT_WIDTH -1) begin
ii = 0;
calc_completed <= 1;
end else begin
ii = ii +1;
end
end else begin
jj = jj +1;
end
end
PUSH_OUT:
begin
data_out <= dout_wire;
done <= 1;
end
endcase
end
end
endmodule