Stats

  • Locked Locked
  • Replies 0
  • Subscribers 62
  • Views 9839
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

RTL Design of SPI

swe

Hello Everyone,

I am new to this forum, so, please advise in case of any mistakes.

I am trying to work on a self-project wherein I intend to develop an RTL Design of SPI using SystemVerilog. I have read the specification sheet, however, I need some guidance as to how should I implement it.

I know there is a master and a slave, but when I looked at the specs sheet, there is a block diagram. Looking at the block diagram is very confusing.

May I have some guidance as to how should I move ahead? Like some stepwise advice as what should I start implementing first and what second and so on...

I am not asking for any code, just general advice.

Link to the specs sheet I am following:- SPI Block Guide V4 (nxp.com)

Thank you for reading and for your valuable time! I really appreciate it.

Swetha. C

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.