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Reading data from a file and assign those into a parametric array in verilogAMS

RFStuff
RFStuff 6 months ago

Dear All,

I want to read data from a file and assign those into a parametric array in verilogAMS.

How can it be done ?

Kind Regards

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  • Andrew Beckett
    Andrew Beckett 6 months ago

    I’m not sure what you mean by “parametric array”. Can you please expand your question with more detail as to what you are trying to do?

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  • RFStuff
    RFStuff 6 months ago in reply to Andrew Beckett

    Dear Andrew,

    I am writing a verilog code for synthesizing a FIR filter with 50 taps.

    Each tap value is represented in CSD (Canonical Signed Digit) format of length 11, so that the tap multiplication with the delayed input data is achieved by simple shifting and signed additions. For example:- a tap value of 0.1621  = 2^-3 + 2^-5 +2^-7 - 2^-9. Its CSD equivalent of length 11 is: 0 -1 0 +1 0 +1 0 +1 0 0 0.

    Now, the CSDs of all 50 tap values is stored in a file as 50 x 11 matrix format.  This should be read into a parameter called tap_CSD anmd used in a generate block as  shown below.

    Note, this code should be for behavioural simulation and should be fully synthesizable.

    int [49:0]  tap_CSD[10:0];

    // Read data from the file into tap_CSD

    ......

    ......

    reg [49:0] data_in[23:0] ;

    ......

    .....

    reg [23:0] r

    wire [49:0] dataMultiplyOut[23:0] ;

    genvar ind1,ind2;

    generate

    for (ind2=0;ind2 <= 50; ind2=ind2+1) begin


           for (ind1=0;ind1 <= 0;ind1=ind1+1) begin

                 if( tap_CSD[ind2][ind1]  == 1 ) begin

                       r= r + data_in[ind2][ind1]  >>  ind1 ;   // Shifting + addition

                 end

                 else if  ( tap_CSD[ind2][ind1]  == -1 ) begin

                     r= r - data_in[ind2][ind1] >> ind1;   // Shifting + Substraction

                end

                assign  dataMultiplyOut[ind2] = r

           end


     end


    endgenerate

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  • RFStuff
    RFStuff 5 months ago in reply to RFStuff

    Dear Andrew,

    Does my previous answer clears your confusion ?

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  • RFStuff
    RFStuff 5 months ago in reply to RFStuff

    Dear Andrew,

    Does my previous answer clears your confusion ?

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  • Andrew Beckett
    Andrew Beckett 5 months ago in reply to RFStuff

    Since this appears to be a pure Verilog question (since you also talk about it needing to be synthesizable) I'll move this to the Logic Design forum since you're more likely to find people with the right expertise there.

    Andrew

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