Can we do synthesis by using variables in generate block

Dear All,

I  want to synthesize a logic  iteratively based on the values of the some variables by using generate construct.

The portion of the generate block is shown below.

Could any body please tell whether it can be synthesized.

Kind Regards,

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parameter NoOfTaps= 4;

integer CSDTapsSignVal[NoOfTaps-1:0][NoMaxCSDBits-1:0];
integer CSDTapsModHornerAddVal[NoOfTaps-1:0][NoMaxCSDBits-1:0];
integer CSDTapsModHornerMultVal[NoOfTaps-1:0][NoMaxMultFactors-1:0];

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reg signed [23:0] Data_in_reg[NoOfTaps-1:0];
reg signed [23:0] r[NoOfTaps-1:0];

genvar i1 ;
integer i2;

generate

for (i1 = 0; i1 <= NoOfTaps-1; i1 = i1 + 1)

     begin
           always @ (Data_in_reg[i1]) begin
                      for (i2 = 1; i2 <= NoOfTaps-1; i2 = i2 + 1)
                      begin
                               if(CSDTapsSignVal[i1][i2] != 0) begin

                                    r[i2] = ( (Data_in_reg[i1] >> CSDTapsModHornerAddVal[i1][i2-1]) ) + ( (Data_in_reg[i1] >> CSDTapsModHornerAddVal[i1][i2]) );      // Shift and Add Iteratively

                               end

                      end

          end
   end
end
// end
endgenerate