Genus Synthesis not preserving register for sequential logic with pragma.

Hi All,

I am using /*cadence preserve_sequential */ pragma to preserve reg type in sequential logic and using "// cadence keep_signal_name clkdiv13 syn_keep=1" to preserve a wire named clkdiv13 in the Verilog design. Upon synthesizing the design with Genus Synthesis Solution I can see that netlist does not retain clkdiv13 wire or it changes the name. Also, Genus changes reg type signals used in sequential logic to wire.

NOTE: I have used "// cadence keep_signal_name xyz syn_keep=1" pragma for other wires and I am able to see them in the synthesized netlist.

1st snapshot shows the Verilog RTL code. 2nd snapshot shows synthesized netlist.

Thanks!

Richa