Decoder standalone synthesis in Genus

module decoder(address,En,add);
    
    input En; // Active high enable
    input [7:0]address;
    output reg [255:0]add;
    integer i;
    
    always@(address or En) begin
        //add[256] = 0;
        if (En) begin
            
            for(i=0;i<256;i=i+1) begin
                add[i]=(address==i)?1'b1:1'b0;
            end
            
        end
        else 
            add = 256'b0; 
        
    end

endmodule

#########################################

## check library units for lf kit using
#report_lib lf11isdhvt7s_worst.lib
## the set_units command below reiterates the defaults for this kit. 
#set_units -capacitance 1.0pF -resistance 1.0kOhm  -time 1.0ns   -voltage V -current uA
## dynamic energy unit pJ Leakage Power unit pW
## .lib area units are equal to .lef area units.

#########################################
### Clock  definition and modelling
#########################################
### Clock - compare clk constraints to connect modules in ADE
#create_clock [get_ports clk]  -name vclock  -period 50  

# Create Virtual clock

create_clock -name vclock  -period 50 
#create_clock -name vclock  -period 5

#report the new clocks
report_clocks

#Constrain the paths
report_timing -lint

# Model the clock
# Clock tree delay (clock network latency), the external clock delays (clock source latency, the skew, the jitter, the transition time
# All the above can be modeled by 1- set_clock_latency,2- set_clock_uncetainty, 3- set_clock_transition
# SDC commnad use a time unit of ns, however Gebus internally uses a time unit of ps
### clock source insertion delay model

#set_clock_latency -source 8  [get_clocks vclock]
#set_clock_latency -source 0.8  [get_clocks vclock]

### clock network insertion delay model
#set_clock_latency -min 0.2 [get_clocks vclock]
set_clock_latency -min 2 [get_clocks vclock]
#set_clock_latency -max 1  [get_clocks vclock]
set_clock_latency -max 10  [get_clocks vclock]


### Clock transiston model
#set_clock_transition -min 0.3 [get_clocks vclock]
#set_clock_transition -max 2 [get_clocks vclock]
set_clock_transition -min 3 [get_clocks vclock]
set_clock_transition -max 20 [get_clocks vclock]

### clock uncertainty model
### Clock jitter (max=0.15, min=0.1) + Clock Skew (max=0.35, min=0.3)
#set_clock_uncertainty -setup 0.5  [get_clocks vclock]
#set_clock_uncertainty -hold  0.4  [get_clocks vclock]

set_clock_uncertainty -setup 5  [get_clocks vclock]
set_clock_uncertainty -hold  4  [get_clocks vclock]

# Note: Lower jitter and skew at min corner

set_ideal_network [get_ports En]
#set_fale_path -rise_from [get_ports En]
#########################################
### IO constraints
#########################################
### set external delays - assume large proportion of clk period
### e.g. 50% of clk period for an IP block
#########################################
### inputs
#########################################
#set_input_delay -max 2.5  -clock vclock [remove_from_collection [all_inputs] vclock] -network_latency_included
#set_input_delay -min 0.1 -clock vclock [remove_from_collection [all_inputs] vclock] -network_latency_included
set_input_delay -max 25  -clock vclock [remove_from_collection [all_inputs] vclock] -network_latency_included
set_input_delay -min 1 -clock vclock [remove_from_collection [all_inputs] vclock] -network_latency_included

# Drive resistance of all inputs except clk
set_drive -max 1    [remove_from_collection [all_inputs] vclock]
set_drive -min 0.01 [remove_from_collection [all_inputs] vclock]
# Re-define the drive resistance (values taken from simulated output resistance of the comparator) of comp
set_drive -max 1 [get_ports address]
set_drive -min 0.1 [get_ports address]
set_drive -max 1 [get_ports En]
set_drive -min 0.1 [get_ports En]

#set_driving_cell  -max -lib_cell BUF_X20 -library "lf11isdhvt7s_worst" -pin Z [all_inputs]
#set_driving_cell -max -library "lf11isdhvt7s_worst" -lib_cell  BUF_X20 -pin Z [all_input]
#set_driving_cell -min -library "lf11isdhvt7s_worst" -lib_cell  BUF_X1 -pin Z [all_input]


#########################################  
# Additional constraints on analog inputs:
#########################################  
# 1) Ensure it feeds into only one cell (simplification for simulation)
#    So that the input is buffered before being used by multiple downstream cells
#set_max_fanout 1 [get_ports address]
#set_max_fanout 1 [get_ports En]
# 2) Constrain the input capacitance below a limit
#    So that it doesn't overly load the comparator
# **** May want to tweak this value for max_cap ****
#set_max_capacitance 0.2 [get_ports address]
#set_max_capacitance 0.2 [get_ports En]

 
#########################################  
### outputs
### equal delays for unequally sized (loaded) switches
### don't worry about the uneven loading for now... think gate caps will be small. 
#########################################
#set_output_delay -max 2.5  -clock vclock [all_outputs] -network_latency_included
#set_output_delay -min 0.01 -clock vclock [all_outputs] -network_latency_included
set_output_delay -max 25  -clock vclock [all_outputs] -network_latency_included
set_output_delay -min 0.1 -clock vclock [all_outputs] -network_latency_included

set_load -max -pin_load 1.0  [all_outputs]
#set_load -max -pin_load 0.1  [get_ports *add*]
set_load -min -pin_load 0.001 [all_outputs]

# All the output paths are constrained and it can be verified by
report_timing -lint

#########################################  
### Electrical Design Rule Constraints
### check specification in library
#########################################
set_max_transition 1 [all_outputs]
set_max_transition 1 [all_inputs]

report_timing -lint
# to check input drives are applied
report_port -driver *
# check the output loads are applied
report_port -load *

# check that input output delay constrains are applied
report_port delay *
#########################################
# 5% WC OCV Timing Derate
# For local cell and interconnect delay variation
#########################################
set_timing_derate -early 0.95
# Derate applies to cell and incterconnect delays


# Note: These will effect the quality of optimisation
#group_path -name in2reg  -from [all_inputs]
#group_path -name reg2out -to   [all_outputs]
#group_path -name in2out  -from [all_inputs]  -to [all_outputs]