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Genus: Generated netlist doesn't define subckts

Anas2023a95

Dear all, 

I'm trying to perform an LVS check using Calibre between a layout that was generated by Innovus and the initial netlist generated by Genus. However, once I hit Run LVS on Calibre, it reports the following warnings and recommends to stop the process:

Source netlist references but does not define more than 10 subckts:
DFD1BWP7T
DFKCND1BWP7T
DFKCNQD1BWP7T
DFKSND1BWP7T
DFQD1BWP7T
IND2D0BWP7T
INR2D0BWP7T
INVD0BWP7T
INVD2P5BWP7T
IOA21D0BWP7T
... (and more)

If I proceed the LVS process it shows lots of errors as shown in the following image:

Why Genus doesn't include the definition of those sub circuits in the generated netlist? Is this related to Flat/Hierarchy netlisting? 

I have included my Genus scripts as well as the generated netlist in the attachments (and here - if attachment don't work).

Many thanks,

Anas

  • Hi Anas,
    I think there is a general misunderstanding here about the type of check you want to do.

    LVS checks that every single transistor in an input netlist can be found with the same size in the layout. So the schematic and layout should be topologically equivalent.

    However, during physical design you will do many transformations on the initial netlist - sizing of cells, adding clock tree, to name a few.

    What you want to check in this case is the logical equivalence of the input netlist and the final netlist after place-and-route.

    This is called logic equivalence checking and its done by tools such as Conformal.

    - Dimo

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