I'm currently trying to explore the verilog simulation option in cadence.
One thing that comes to my mind that if there exists a way in cadence workflow to dump selected register/wire's waveform during the simulation.
Are there any additional tools needed apart from xcelium, is there a tutorial or specific training course for this aspect. I glance through Xcelium Simulator Course Version 22.09, but it seems not having related context.
I know in Synopsys's workflow, it can be realized using verdi & fsdb in the command line as follows:
Thanks in advance!