LEC (Logic Equivalence Check) hang debug

For my small register bank design( with 50 flops and some address decoder logic) after synthesis when I try to run lec the rtl2fvmap lec hangs at the step

write_hier_compare_dofile hier_tmp2.lec.do -verbose -noexact_pin_match -constraint -usage \
-replace -balanced_extraction -input_output_pin_equivalence \
-prepend_string "report_design_data; report_unmapped_points -summary; report_unmapped_points -notmapped; analyze_datapath -module -verbose; eval analyze_datapath $DATAPATH_SOLVER_OPTION -verbose"

the below is the terminal. It is stuck at this state for several hours.

--------------------------------------------------------------------------------
// Starting hierarchical dofile generation ...
--------------------------------------------------------------------------------
// Total Matching Module Instance Pairs = 3
// Module Instantiation Ratio in Golden = 1.00
// Module Instantiation Ratio in Revised = 1.00
// Gathering Instance Boundary Information ...
// Extracting Constraints in Golden ...

By modifying the do file step to below(removed options -constraint and  -input_output_pin_equivalence) the lec passes in 2 minutes. I think these 2 options help remove false failures. Since my lec is passing I don't need them I guess. Am I right?

And is this a know bug in the lec tool?

write_hier_compare_dofile hier_tmp2.lec.do -verbose -noexact_pin_match -usage \
-replace -balanced_extraction \
-prepend_string "report_design_data; report_unmapped_points -summary; report_unmapped_points -notmapped; analyze_datapath -module -verbose; eval analyze_datapath $DATAPATH_SOLVER_OPTION -verbose"

The lec also passes without needing any modification if I reduce the flops to 30 or increase it to 70 etc.