I want to plot the phase noise of my closed-loop PLL where there were digital blocks in verilog and analog blocks in transistor level. I used AMS as the simulator, but I colud not find the PSS and Pnoise options in AMS. How colud I plot the phase noise diagrams of such kinds of mixed signal systems?
Thanks for your help!
You can't do this currently. It would be theoretically possible if anything handled in the digital engine remained static during the PSS - so you could use the AMS simulation to configure the design, and then you run the PSS/Pnoise on the analog portions of the circuit. If however you wanted the digital portions of the design to be active, the problem is then that the digital portions would be a "hidden state" for PSS - the PSS algorithms would not have visibility of the state of the digital nodes.
Commonly complex PLLs use sigma-delta modulators (i.e. a Fractional-N PLL rather than Integer) and are consequently not periodic - so that would be a further reason why you couldn't do this (even if the hidden state issue had been solved).
However, even the first option is not possible currently.
There has been some thought about this - but we really need a customer partner who we can work with to identify the precise requirements and how this would work. So I would suggest that you contact customer support and then we can file an enhancement request with R&D capturing your needs.