I have been working with a digital block made in SystemVerilog and instantiated into a larger analog design. The HDL was imported into the corresponding cell views in virtuoso and symbols were generated for all hierarchical cells. After running synthesis and P&R the resulting netlist and layout was also imported into virtuoso also into the respective views. This created a problem though.
RTL compiler had to create several internal hierarchical pins to handle the scan chain signals, of course not present in the original design. The same applies to encounter, that created the buffered versions of the clock and reset pins. Because of these pins though, the new views and the original SystemVerilog views do not match. This kills the netlister when it tries to put things together for VerilogAMS when we try to get a mixed digital/analog simulation. It is odd as the tool could have simply put the SystemVerilog files together and they would have worked, or netlisted the schematics down to transistors and they would have worked too.
What is the best way to handle this. Flattening the design would eliminate the problem as the pins are between different internal hiearchical levels, but kills all benefits from hierarchical design. In my view ideal would be able to tell the netlister to simply ignore the missing pins when using the SystemVerilog views in the analog design but of course a full netlist would be needed for UltraSim or spectre.
Anyone have any idea?
I did not get any responses here, probably was the wrong forum. But in case someone wants an answer, I later tried the Mixed signal forum and got the following solution
thanks for sharing the response.
Can anyone tell me how do I give bits as input ie 100001010111.
Is der ny ways..
pls do the needful
Can you please elaborate on the issue? What tool are you using? Is this an RC question? Virtuoso? EDI? General HDL? It is unclear what information to me what information you are looking for