I have a mixed schematic, mostly analog but with some embedded digital controllers. The digital parts were made in SystemVerilog and imported into the correct views in virtuoso together with the schematics. Then using RC and Encounter the schematics and layout views were generated and also imported into the database. The problem is some inconsistencies came up.
RC added pins for scan chain and Encounter had to buffer the clock trees and created the respective pins as well (clk__L1..., etc). These do not show up in the top level of the digital schematics, only between the internal blocks. Being these new pins do not exist in the RTL, anytime I open the SystemVerilog views I get error messages back from the tool stating the pins are not consistent with the symbol. If I just send it all to UltraSim or VerilogAMS with the netlist views it works fine, but when I try to use the SystemVerilog views with the schematics to run VerilogAMS the netlister quits with an error. The netlister will not run if the views do not match even though the SystemVerilog files do not need these extra pins.
I guess the simplest solution would be to change the RTL by adding these missing pins as dummy pins. A bit anoying as it would start cluttering the design and also would require some manual work after every change to remove the old added pins, add the new ones (as the names change in every run) and recheck all schematics and symbols.Remove the added pins does not sound like a solution either as they are in the layout and therefore LVS is going to expect to find them.
Being these are not new concepts I would think Cadence already has something in place to handle these issues of mixed environments. Anyone have any ideas?
which IC and EDI version do you use ? Since you're talking about layout views I assume you work on an Open Access Database.
Is you're PDK Mixed Signal enabled - means do you have your technology LEF available as an OA library referencing the Base PDK?