Is there a reason why you're using the really old "verimix" (spectreVerilog) simulator as opposed to "ams" (AMS Designer) which is much newer and supports far more in terms of language support? spectreVerilog is essentially obsolete...
I'm not sure of the reason for the failure (without doing research that I don't have time to do right now unfortunately) - if you really can't use AMS Designer, I'd suggest you contact customer support.
I have changed my simulator to ams. Now iam having verilogams codes and schematic in my design.Netlist generation is working well. But elaboration is skipped. Can you suggest any idea when this happens. Can you also give me an example stimulus file for simulation to undertand the syntax.
Iam able to get the elabotaion. But during simulation iam getting x/z in digital domain which cannot be converted in analog domain.
I think this is because i didn't provide any stimulus file. So, please provide me an example stimuls file to know the syntax. If it is due to timing, please suggest me a solution.
Not sure what "stimulus file" you're talking about. It may be a spectre syntax file, or you may want to have some Verilog code, or you may just put sources from analogLib in to drive your circuit. Your mileage may vary.