I'd like to model a resistor in verilog ams using wreal. That is, I need the equivalent of the "tran" primitive that exists in vanilla verilog.
module res (p,n);
//need a model here, something like tran t1(p,n)
I've tried to check the inouts for the `wrealZState to determine what port is actually actually driving and set the signal direction accordingly but I couldn't get good simulation results.
Has anyone already solved this problem?
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It's not that obvious what you are trying to do - modelling a resistor with wreal is not really possible unless you're prepared to compromise - since you are only modelling the potential or the flow (not both) - and a resistor would normally be implemented using a conserving approach (i.e. V=I*R). So you may have to make clear what compromise you are prepared to make.