I'd like to model a resistor in verilog ams using wreal. That is, I need the equivalent of the "tran" primitive that exists in vanilla verilog.
module res (p,n);
//need a model here, something like tran t1(p,n)
I've tried to check the inouts for the `wrealZState to determine what port is actually actually driving and set the signal direction accordingly but I couldn't get good simulation results.
Has anyone already solved this problem?
I appologize. I guess we should start a AMS Verification forum, everytime I want to post something I am not sure were to place it.
As for the resistor, all I needed was a wreal bidir net. Problem solved! I do have a continuous time view of that cell which is a conservative resistor model but sometimes I want to switch my system to discrete time (event driven) to speed up simulation. A bidir net does not care if the information (real number) is a potential or a flow.