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  3. How to setup Cadence ADE to simulate basic digital blocks...

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How to setup Cadence ADE to simulate basic digital blocks successfully

bhl3302
bhl3302 over 12 years ago

Hi, I am using Virtuoso IC6.1.5 with IBM BiCMOS8HP technology. It runs well in ADE for analog design. But when I imported digital library of this technology,draw a basic circuit schematic with AND block, and include .scs file and verilog file for this AND block, the simulation was not successful. The error message showed here is

-------------

 *INFO* (icLic-25) License Analog_Design_Environment_XL ("95210") was used to run ADE L.

Loading analog.cxt
Loading asimenv.cxt
Loading spectrei.cxt
Loading relXpert.cxt
Loading par.cxt
Loading socket.cxt
Loading alvs.cxt
t
sevLoadState('sevSession1)
>
hiiSetCurrentForm('sevLoadForm1)
t
hiFormDone(sevLoadForm1)
Loading devCheck.cxt
t
t
sevNetlistAndRun('sevSession1)
Delete psf data in /ece/grad/yhuang85/simulation/4_130818/spectre/schematic/psf.
generate netlist...
Loading spectreinl.cxt
Loading seCore.cxt
Begin Incremental Netlisting Aug 18 21:50:35 2013
WARNING (OSSHNL-145): Incremental netlisting is not possible since the netlist in this run directory
was generated using a previous IHNL version which is incompatible with the
current IHNL version. Therefore re-netlisting the entire design using the
current IHNL version.
 
ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'spectre cmos_sch cmos.sch schematic veriloga', for the
instance 'AND2_I0' in cell '4_130818'. Either add one of these views to the library 'digital_library',
cell 'AND2_I' or modify the view list to contain an existing view.
 
End netlisting Aug 18 21:50:35 2013
ERROR (OSSHNL-514): Netlisting failed due to errors reported before. Netlist may be corrupt or may not be produced at all. Fix reported errors and netlist again.
      ...unsuccessful.

 

-------------- 

 

Could anyone teach me if there is any mistake I make in ADE setup in order to run this circuit? Thank you very much! 

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  • Andrew Beckett
    Andrew Beckett over 12 years ago

    If your digital library only has verilog descriptions, you won't be able to simulate it with spectre; spectre is an analog circuit simulator and like other SPICE-like simulators, doesn't handle logic level verilog descriptions.

    For that you'd need to use "AMS Designer" (ams as the simulator in ADE). I suggest you start with the AMS Designer Tutorial in the documentation.

    Regards,

    Andrew.

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  • marten
    marten over 11 years ago

    Hi there,

    what files are needed to run Spectre on digitial elements (like NAND, NOR,.. ) ? We have a PDK installed but I am not sure if the necessary files for analog sim of the digital elements are included. Could you give me a kick in the right direction ?

    Best regards,

    Marten

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  • Andrew Beckett
    Andrew Beckett over 11 years ago

    Does the library of digital elements have schematics?

    Andrew.

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  • marten
    marten over 11 years ago

     Hi,

     yes there are schematics available for nearly every element. Also I found a bunch of *.scs-files within the PDK.

     Marten

     

     

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  • Andrew Beckett
    Andrew Beckett over 11 years ago

    You're probably good to go then. You might want to check with the provider though - they ought to document what they support...

    Regards,

    Andrew.

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  • marten
    marten over 11 years ago

     Thanks for the quick reply!

    Maybe you can give a short overview how to load these files into ADE ?

    Regards,

    Marten

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  • Andrew Beckett
    Andrew Beckett over 11 years ago

    If you have schematics, then I wouldn't have thought you need the .scs files if they are describing the same cells.

    As I said, you should ask the provider precisely what you are supposed to do as this can vary from supplier to supplier. I can't really guess without seeing what information you have.

    Regards,

    Andrew.

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  • marten
    marten over 11 years ago

     Okay I will do so.

    Thanks for your help!

    Regards,

    Marten

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