ploting/saving Verilog-A variables with AMS simulator using Ultrasim Solver

Hi,

I am trying to save the verilog-A variables in using AMS with Ultrasim solver, as the saveahdlvars doesn't work, I used .probe statement as per this http://www.cadence.com/forums/p/14932/26102.aspx discussion. But the suggestions works well when the simulator is pure ultrasim. When I change to AMS with Ultrasim, the .probe statement doesn't seams to work.

I used, simulator lang = spice lookup=spectre 

          .probe tran all(I0.I2.I*.I*.I2)

I included the file containing the above using setup --> simulation files --> include files option in ADE. But when I create the netlist, the file is not at all available in the netlist. 

 What is the mistake here? Someone help!!