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  3. digital gate delay in AMS design environment

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digital gate delay in AMS design environment

apple419
apple419 over 11 years ago
Hi,

   I am doing a mixed-signal simulatio in AMS design environment. The digital section is at gate-level. The logic gates are described by Verilog. The default delay is specified for each gate in the Verilog description.

   The simulation went well but there is one problem. The digital section simulation result does not show meaningful timing. In that I mean the delay through each gate is the default one specified in the Verilog. It does not change with the load it is driving. The loading effect, or the wire load effect, is not considered. 

   I googled online and I realized that I may need a SDF file. With this file, the simulator will include the loading effect into the digital simulation. 

   My question is how to generate this SDF file? How is it used in the AMS environment?

   By the way, the digital section is manually designed. It is not a HDL-based design. Some online article says while compiling the HDL description, the SDF can be generated... 

   My platform: Cadence Virtuoso IC6.1.5. The simulator is ams in ADE.  

Thanks

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  • Andrew Beckett
    Andrew Beckett over 11 years ago

    Typically you'd use a delay calculator (often part of a static timing analysis tool such as EPS or Tempus or PrimeTime (from Synopsys) to generate SDF).Then in ADE (with "ams" as the simulator), use Simulation->Options->AMS Simulator, and then use the SDF tab.

    Regards,

    Andrew.

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