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AMS simulation with VCD input file

Abhishek D

Hi,

            I am running an ams simulation with VCD input file. I did this with config view with ams template . I see my inputs are not correct. They are some random pwl signals. If I see my input file using simvision -wave <vcdFileName.vcd>, I see the signals are correct. I have attached signalInfo file with VCD file. I have run the same VCD with spectre, it works fine. But now I am using a verilog block whose job is to force some digital signals on the fly, that's why I have moved to ams simulator. After spending a lot of time I am not able to debug what is causing this issue.

           Please help if someone has an idea what exactly I might be doing wrong. 

 

Best Regards

Abhishek 

  • Hi Abhishek,

    I suspect this is because you have the VCD file driving digital nets. There is a long-standing limitation that VCD and vector files can only drive analog nets - and there's a CCR for this, 513270. You might expect that since VCD (Verilog Change Dump) is a digital format, it could drive digital nets, but the functionality actually comes from the analog simulator part (either spectre or Ultrasim). So it's a bit of an unexpected limitation, but that's how it is right now.

    If this matches what is going on for you, the workaround is to connect resistors to each digital net and then drive those. Of course, that may impact your simulation performance if you don't have many (or any) electrical nets otherwise.

    You may want to contact customer support and request this for yourself (please reference the CCR number) - that way a duplicate CCR can be filed to indicate your need.

    Kind Regards,

    Andrew.

  • Hi Andrew,

                          Thanks for your reply. But I would like to make this thing into you attention that I am using VCD file with signalInfofile only for analog signals. So whenever I had to do it I did with spectre. It works all the time. My requirement was now to force few signals on the fly and  that can be done only with simvision with digital outputs. So what I did , I made 2 line verilog code which has only ouptut and default value 0. While simulating I used  -access +rwc in ams options.  So when I run my simulation everything will go in the previous manner as I was doing in pure analog mode spectre config simulation when I will reach to steady state I will force some signals on the fly and  see the effect.

                            But what is happening is very strange. I have one clock ( coming from VCD - will go to  analog net) which goes from 0 to 1.8V up and down. This signal comes as a pwl signal and stuck and 1.2V and it stays there forever. I am using clock signal as a input to a d flip flop which at positive edge transfer my vcd input to my circuit ( analog). Now clk and all other signals coming from VCD file are stuck at 1.2V so effectively nothing is happening in my circuit. I have tried my best to explain my situation. Please let me know If you can help me.

  • I think it's best if you report this to customer support. Sounds like a bug to me. We'll almost certainly need to see your data.

    Regards,

    Andrew.

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