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AMS simulation using ADE. How to save internal verilog module signals.

weebey
I am running an AMS simulation using ADE and am having troubling saving some of the signals in my verilog module. I created and imported a .csv file with the list of outputs I wanted to save. However, only some of the nets are saved. All of the saved nets were wires. None of my registers were saved. And not all of the wires were saved. I'm not sure how to fix this. Can anyone help me out. Thanks.

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