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Mixed-signal LVS netlist from schematic

bdjones1
Hi,

I need some help running mixed-signal LVS on a 180nm CMOS design using IC 5.1.41 and Calibre LVS.

The top level design is a Cadence schematic that contains several analog blocks and a nested digital block.  I have a verilog view and symbol of the digital block, from which I generated a v2lvs spice netlist.  The v2lvs netlist includes the spice file from the IP library provider defining the standard cells.   The v2lvs netlist and digital block layout are LVS clean.  

I need to get LVS clean at the top level.  I'd like the Cadence netlister to use the v2lvs netlist for the digital block, but I'm struggling to get this to work.  I've tried importing the v2lvs netlist, but it doesn't like the include statement to the standard cell definitions.  I tried deleting the include statement, and adding empty subckt definitions for all the std cells, but CDL In still doesn't recognize the primitive cells.  

I've also tried importing the verilog (File > Import > Verilog), but it only imports the code as a functional view, and I haven't been able to get it to generate a schematic view containing the standard cells.  I've set "Import Structural Modules As" to schematic, but that seems to have no impact.

Any suggestions on generating a LVSable netlist of a nested digital block?
Thanks!!
Brian 

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