AMS ncvlog error

 I am new in using ncvlog

I have an error when i am trying to simulate simple inverter

          |
ncelab: *E,CUVMUR (./ihnl/cds0/netlist,19|10): instance 'test.top@Inv_1<module>.PM0' of design unit 'pmos1v' is unresolved in 'worklib.Inv_1:verilog'.
nmos1v  NM1 ( .D(Vout), .B(cds_globals.gnd_), .G(Vin),
          |
ncelab: *E,CUVMUR (./ihnl/cds0/netlist,21|10): instance 'test.top@Inv_1<module>.NM1' of design unit 'nmos1v' is unresolved in 'worklib.Inv_1:verilog'.
ncxlmode: *E,ELBERR: Error during elaboration (status 1), exiting.

my pdk which is GPDK45n 

Any help please .

 I merged your two duplicate posts together (the forum guidelines tell you not to do this).

It's not clear whether you are running AMS Designer, ncvlog, or nc-verilog. I suspect from the filenames mentioned, you're using the NC Verilog integration rather than AMS Designer. If so, it's hardly surprising because it won't know how to deal with a transistor - you'll need to either stop at a verilog description of your cell, or use AMS as the simulator in the Analog Design Environment (which can simulate the transistors with an analog solver, and the digital parts with an event-driven engine).

Regards,

Andrew.