Verilog-A module instantiating

I just used this and it worked fine:

`include "disciplines.vams"

module hierLower(a,b,f);
inout a,b,f;
electrical a,b,f;
parameter real r=1k;

analog begin
//  if ($port_connected(f)) begin
//    $strobe("f is connected\n");
//  end
  V(a,b)<+I(a,b)*r;
end

endmodule


`include "disciplines.vams"

module hierUpper(c,d);

input c,d;
electrical c,d;

//hierLower R1(.a(c),.b(e),.f(n));
hierLower R1(.a(c),.b(e));
hierLower R2(.a(e),.b(d));

endmodule

So my guess is that the syntax error is probably in something before the line it mentions, in the part you omitted from your post. Maybe a missing semi-colon?

Andrew.

I have got exactly the same error.

Error (VACOMP-2259): " parameter gain =<<--?  1;"

here is my code:

Module CCVS(pout,nout,pin,nin);parameter gain = 1;

analog V(pout,nout) <+ gain * I(pin,nin)

endmodule

It is so simple but I do not know where is the issue.

Well, there are several things wrong with your code, but I don't get the error you show - I'm assuming you haven't got precisely what you posted as your code. For example, at least:

1. The "Module" should be "module" (the language is case sensitive).
2. You are using the V() and I() access functions, but don't declare any disciplines (`include "disciplines.vams")
3. You didn't specify the discipline of the pout,nout,pin,nin signals
4. You're missing a semi-colon on the end of the contribution statement.

All in all, it should be this:

`include "disciplines.vams"
module CCVS(pout,nout,pin,nin);
electrical pout,nout,pin,nin;
parameter gain = 1;

analog V(pout,nout) <+ gain * I(pin,nin);

endmodule

Regards,

Andrew.

Sir I have a similar error,

ERROR (VACOMP-2259): ""sign_multply="0<<--? ;"
"/home/buet/cds_work/memristo_vteam/vteam/schematic/veriloga.va", line
171: syntax error.
ERROR (VACOMP-2259): ""sign_multply="1<<--? ;"
"/home/buet/cds_work/memristo_vteam/vteam/schematic/veriloga.va", line
173: syntax error.
ERROR (VACOMP-2212): "sign_multply=<<--? 0;"
"/home/buet/cds_work/memristo_vteam/vteam/schematic/veriloga.va", line
177: Encountered undeclared identifier: sign_multply. Declare the
identifier before using it.
ERROR (VACOMP-2212):
"w=dwdt*dt*(1-pow(2*w/D-1,2*p_coeff))+w_last+sign_multply*<<--?
p_window_noise;"
"/home/buet/cds_work/memristo_vteam/vteam/schematic/veriloga.va", line
183: Encountered undeclared identifier: sign_multply. Declare the
identifier before using it.
ERROR (VACOMP-1552):
"/home/buet/cds_work/memristo_vteam/vteam/schematic/veriloga.va", line
183: Encountered left operand of type *undef* for operator `*'. Specify
a real or an integer type operand instead.
ERROR (VACOMP-2259): "if (stp(-I(p,n))<<--? == 1) begin"
"/home/buet/cds_work/memristo_vteam/vteam/schematic/veriloga.va", line
190: Encountered an undefined function stp. Check the spelling of the
function or define the function before using it..

sign_multply=0;
if(w==0) begin
sign_multply=1;
end
end
if (sign(I(p,n))==-1) begin
sign_multply=0;
if(w==D) begin
sign_multiply=-1;
end
end

w=dwdt*dt*(1-pow(2*w/D-1,2*p_coeff))+w_last+sign_multply*p_window_noise;

end // Jogelkar window

// Biolek window
if (window_type==2) begin

if (stp(-I(p,n)) == 1) begin
stp_multply=1;
end
if (stp(-I(p,n)) == 0) begin
stp_multply=0;
end

I struggle to see what on earth this has to do with this thread - other than both being Verilog-A related.

The errors are completely different and the forum guidelines ask you not to append on the end of old threads (and provide the versions you're using, and give enough information to fully describe the issue, none of which you've done).

However, in this case the errors are pretty clear - it's saying you've not declared:

1. sign_multply
2. The function stp()

Since you've not provided the entire model but just parts of it, debugging the rest is rather difficult - but presumably you're going to have to fix those two fundamental issues first!

Anyway, I suggest you fix those, and if you have any remaining issues, create a new thread with the full information as suggested by the forum guidelines.

Andrew