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AMS simulation questions

Octavian

I have a top level verilog testbench instantiating an analog spectre module (subckt). I can run a transient simulation with the Incissive irun flow but I could not figure out how to do the following:

- sample an internal voltage/current in the analog module and use that in the verilog code to make a decision:

if ( V(I0.I0.I0.analog_node) > 1 )

// startup is done 

 - set the voltage on an internal analog node from the verilog code. 

 - specify the simulation end time from verilog only. I have a $finish statement in verilog but the simulation does not run without a tran statement in the analog code. For now I just made the tstop paratemeter for the tran statement very large so the $finish gets called much earlier, but I'm wondering if there is a better way.

 Any help is appreciated. 

  • I made some progress on this but I could still use some help. I gave up on using a VerilogD testbench (due to limited support for real numbers) and focused instead on SystemVerilog and Verilog-AMS.

    The out of module refereces (OOMR) work with the setup listed below. It seems that everything is fine and E2R/R2E conversion blocks are inserted if I use a wreal buffer module, but only logic levels (E2L/L2E conversions) are passed if I use assign statements. Does anybody know how to force the the E2R/R2E conversions for OOMR's and assign statements?

    Also I used VerilogD testbenches with other co-simulation tools previously and they had built in tasks (i.e. $snps_get_voltage) for OOMR access accross simulation domains. Is there something equivalent available in the Cadence flow?  

    ----------------------

    top.vams 

    ---------------------- 

    module real_buff(i,o);

        output wreal o;

        input wreal i;

        assign o=i;

    endmodule

     

    module testbench ;

     

        wreal rtop;

        wreal rmid;

        real src;

        wreal sense;

        assign rtop = src;

     

        //assign sense = rmid;

        //assign sense = I0.rmid2; // does not work (assigns logic connection)

        //real_buff b2(.i(I0.rmid2), .o(sense));

        //assign I0.rtop2 = src; // does not work (assigns logic connection)   

        real_buff b3(.i(src), .o(I0.rtop2));

        real_buff b2(.i(I0.rmid3), .o(sense));

     

        res_ladder I0 (.rtop(rtop),.rmid(rmid));

     

        initial begin

            src=0.0;

            #10 src=3.0;

            #10 src=1.0;

            #10;

            $finish;

        end

     

        always @(sense) $display("%t: sense has changed to %0f", $time, sense);

     

    endmodule

    -------------------------

    res_ladder.scs 

    --------------------------

    subckt res_ladder rtop rmid

    r1 (rtop rmid) resistor r=10k

    r2 (rmid rmid2) resistor r=10k

    r3 (rmid2 0) resistor r=10k

    r4 (rtop2 rmid3) resistor r=10k

    r5 (rmid3 0) resistor r=10k

    ends

    --------------------------------

    amscf.scs 

    -------------------------------- 

    timeDom tran stop= 30u

     

    include "res_ladder.scs"

     

    amsd {

            portmap subckt=res_ladder

            config cell=res_ladder use=spice

            ie vsup=1

    }

    ----------------------------------------

    > irun -access +rw -solver spectre  -timescale 1ns/100ps -iereport -autospiceoomr amscf.scs top.vams

    ----------------------------------------- 

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