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mixed signal simulation

KUMARJAYA
is it possible to simulate verilog netlist in cadence virtuoso?how to bind the standard netlist cell to the corresponding code?
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  • There's a tutorial in the installation, and covered in the AMS documentation. 

    In the CIW, do Help->Virtuoso Documentation. In the Documentation Browser (left pane of the help system) expand IC6.16 (or similar), AMS Environment and then Virtuoso AMS Designer Environment Tutorials. This tells you where to find various tutorials on getting started with AMS Designer.

    Regards,

    Andrew.

Reply

  • There's a tutorial in the installation, and covered in the AMS documentation. 

    In the CIW, do Help->Virtuoso Documentation. In the Documentation Browser (left pane of the help system) expand IC6.16 (or similar), AMS Environment and then Virtuoso AMS Designer Environment Tutorials. This tells you where to find various tutorials on getting started with AMS Designer.

    Regards,

    Andrew.

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